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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.2
Protocol Timing and Commands of Single Pin Interface
During the communication mode, the output level is defined by the external pull up resistor R Communication . The output driver of the device is in tri-
state. The bit coding (see Figure 18) has been chosen in order to allow the continuous synchronization during the communication, which can be
required due to the tolerance of the internal clock frequency. Figure 18 shows how the different logic states '0' and '1' are defined. The period of
the clock T CLK is defined with 222.2 ns.
The voltage levels V H and V L are CMOS typical.
Each frame is composed by 20 bits. The 4 MSB (CMD) of the frame specifies the type of command that is passed to the AS5263. The 16 data
bits contain the communication data. There will be no operation when the ‘not specified’ CMD is used. The sequence is oriented in such a way
that the LSB of the data is followed by the command. The number of frames vary depending on the command. The single pin programming
interface block of the AS5263 can operate in slave communication or master communication mode. In the slave communication mode, the
AS5263 receives the data organized in frames. The programming tool is the driver of the single communication line and can pull down the level.
In case of the master communication mode, the AS5263 transmits data in the frame format. The single communication line can be pulled down
by the AS5263.
Figure 12. Bit Coding of the Single Pin Programming Interface
V H
V L
Bit “0”
V H
V L
Bit “1”
T 1
T 2
T 1
T 2
Figure 13. Protocol Definition
T 1 = 128 * T CLK
T 2 = 384 * T CLK
T BIT = T 1 + T 2 = 512 * T CLK
IDLE START
www.austriamicrosystems.com/AS5263
DATA
PACKET
Revision 1.4
COMMAND
IDLE
START
19 - 37
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